Summary:

We are a tight-knit team looking for a Senior Staff Verification Engineer that will verify mixed-signal designs and utilizing Cadence Virtuoso Tool Suite.  In this role, you will work with our analog design team, architects, and system designers to verify products and generate behavior models that will be implemented into leading edge power management solutions for some of the highest performing servers in the world.

Description:

• In this role, you will perform verification of mixed-signal designs using Cadence Virtuoso tools. In addition, you will generate VerilogAMS/System Verilog models with schematic level performance. 
• You will generate simulation workbenches and interpret the results to verify compliance with system level requirements. 
• You will also verify design for test plans and generate RTL codes for products with digital footprints. 
• You will be responsible for Synthesis, place and route with static timing analysis, vector generation and scan insertion.

Requirements:

• BSEE/MSEE with at least 3 years of experience
• Proven experience with Cadence Virtuoso Tools
• Capable of creating schematics and generating netlist for simulation
• Strong understanding of signal flow and boundaries between the analog and digital domains.
• Experience compiling, elaborating, and running mixed-signal simulations
• Strong debugging skills in both the analog and digital domains
• Conversant in Verilog, VHDL, C, C++, and capable of generating scripts
• Experience with DFT (BIST, scan chains, etc.)
• Experience with lab test equipment such as oscilloscope, DMM, power supplies, etc.
• Experience with Microsoft Office Tools (powerpoint, word, excel) and Unix/Linux shell commands and editors